I. Field of the Disclosure
The technology of the disclosure relates generally to snoop-based cache coherency in processor-based systems, and in particular, to maintaining cache coherency in the presence of multiple master devices.
II. Background
Modern processor-based systems may include multiple interconnected master devices (e.g., central processing units (CPUs), graphics processing units (GPUs), processor clusters, and/or hardware accelerators, as non-limiting examples), each of which may access shared data and maintain its own cache of the shared data. To ensure that the cache of each master device within a processor-based system contains the most up-to-date version of the shared data, the master devices may implement bus coherency protocols for maintaining cache coherency among the caches. One class of bus coherency protocols is based on a mechanism known as “snooping.” Using snooping, each master device monitors a bus to detect all read and write requests that originate from other master devices and that involve data that is shared among the master devices. If a master device detects (or “snoops”) a read request for which it has the most up-to-date data, the master device may provide the requested data to a requesting master device (a process referred to as “intervening”). If the master device snoops a write transaction on the bus, the master device may invalidate its local copy of the written data within its cache. In this manner, a consistent view of the shared data may be provided to all of the master devices within the processor-based system.
Under some circumstances, multiple snooping master devices may provide intervention responses to a read request, even though ultimately only one snooping master device can provide intervention data in response to the read request. As a result, it may be necessary to select an appropriate snooping master device to provide intervention data from among the multiple snooping master devices. However, this task may be complicated in processor-based systems in which master devices use caches based on different cache line granule sizes, and/or use different bus coherency protocols that allow intervention under different circumstances (e.g., intervention on a SharedClean cache state). Thus, it is desirable to provide a mechanism for conditionally selecting a master device from among multiple snooping master devices to maintain cache coherency, to provide shorter intervention latency, and to reduce processor power consumption.